1. Technical Field
Exemplary implementations of the herein disclosed subject matter relate generally to semiconductor devices and, more particularly, to a memory device in which when an additional failed block is caused after a primary repair of failed blocks is completed a secondary repair is performed and verification of the secondary repair is carried out.
2. Discussion of the Related Art
As the process scale of manufacturing memory devices, such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc., has been reduced, the number of failed memory cells has increased significantly. A memory cell array of the memory device may include a normal region and a redundant region. Failed blocks found in the redundant region during an electrical die sorting (EDS) test in a wafer stage may be deactivated and not used. Also a primary repair may be performed during the EDS test such that failed blocks found in the normal region may be replaced with redundant blocks in the redundant region.
Additional failed blocks may be caused after the wafer is cut and the cut dies are packaged. In this case, a secondary repair in the package stage and verification of the secondary repair is required